High Speed, Low Power Design Rules for SRAM Precharge and Self-timing under Technology Variations
نویسندگان
چکیده
Due to low-power and reliability requirements, supply voltage is constantly decreasing. On the other hand, high speed operation is required along with increasing memory size. In a CMOS SRAM, power can be saved and cycle time reduced if bit lines are not precharged to VDD. The aim of this work is to analytically derive a model for the design of precharge and self-timing, maintaining the core-cell stability. Stability issues for current and voltage sensing are analytically investigated with respect to local and global process variations. The validity of the model is proven by silicon measurements. Results are extrapolated to future technologies, showing that the ratio of critical precharge voltage to power supply voltage decreases, so that even more power can be saved by proper choice of the precharge level.
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